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<a name="details" id="details"></a><h2 class="groupheader">Overview</h2>
<div class="textblock"><p>This header file contains identifiers and register-level core functions (or macros) that can be used to access the Xilinx SDI RX core. </p>
<p>For more information about the operation of this core see the hardware specification and documentation in the higher level driver <a class="el" href="xv__sdirx_8h.html">xv_sdirx.h</a> file.</p>
<pre>
  MODIFICATION HISTORY:</pre><pre>  Ver   Who    Date     Changes
</p>
<hr/>
<p>
  1.0   jsr    07/17/17 Initial release.
</p>
<h1>vve    10/03/18 Add support for ST352 in C-Stream</h1>
</pre><pre>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:a03ee5488e3a4741dbe0ca82423520d18"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__sdirx__hw_8h.html#a03ee5488e3a4741dbe0ca82423520d18">XV_SDIRX_HW_H_</a></td></tr>
<tr class="memdesc:a03ee5488e3a4741dbe0ca82423520d18"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prevent circular inclusions by using protection macros.  <a href="#a03ee5488e3a4741dbe0ca82423520d18">More...</a><br/></td></tr>
<tr class="separator:a03ee5488e3a4741dbe0ca82423520d18"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2ed5f658c2cce95c1abff6f684b78532"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__sdirx__hw_8h.html#a2ed5f658c2cce95c1abff6f684b78532">XV_SDIRX_SHIFT_16</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:a2ed5f658c2cce95c1abff6f684b78532"><td class="mdescLeft">&#160;</td><td class="mdescRight">16 shift value  <a href="#a2ed5f658c2cce95c1abff6f684b78532">More...</a><br/></td></tr>
<tr class="separator:a2ed5f658c2cce95c1abff6f684b78532"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa01626b56f4a4bb197301ce06c17d33e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__sdirx__hw_8h.html#aa01626b56f4a4bb197301ce06c17d33e">XV_SDIRX_MASK_16</a>&#160;&#160;&#160;0xFFFF</td></tr>
<tr class="memdesc:aa01626b56f4a4bb197301ce06c17d33e"><td class="mdescLeft">&#160;</td><td class="mdescRight">16 bit mask value  <a href="#aa01626b56f4a4bb197301ce06c17d33e">More...</a><br/></td></tr>
<tr class="separator:aa01626b56f4a4bb197301ce06c17d33e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Register access macro definition</div></td></tr>
<tr class="memitem:a361bfcf74a8aa15417629343eccac197"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__sdirx__hw_8h.html#a361bfcf74a8aa15417629343eccac197">XV_SdiRx_In32</a>&#160;&#160;&#160;Xil_In32</td></tr>
<tr class="memdesc:a361bfcf74a8aa15417629343eccac197"><td class="mdescLeft">&#160;</td><td class="mdescRight">Input Operations.  <a href="#a361bfcf74a8aa15417629343eccac197">More...</a><br/></td></tr>
<tr class="separator:a361bfcf74a8aa15417629343eccac197"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad753096703e130b7080880ba43e8fde1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__sdirx__hw_8h.html#ad753096703e130b7080880ba43e8fde1">XV_SdiRx_Out32</a>&#160;&#160;&#160;Xil_Out32</td></tr>
<tr class="memdesc:ad753096703e130b7080880ba43e8fde1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Output Operations.  <a href="#ad753096703e130b7080880ba43e8fde1">More...</a><br/></td></tr>
<tr class="separator:ad753096703e130b7080880ba43e8fde1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a11c28dcf104dea98ffe4e3eef0a600cb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__sdirx__hw_8h.html#a11c28dcf104dea98ffe4e3eef0a600cb">XV_SdiRx_ReadReg</a>(BaseAddress, RegOffset)&#160;&#160;&#160;<a class="el" href="xv__sdirx__hw_8h.html#a361bfcf74a8aa15417629343eccac197">XV_SdiRx_In32</a>((BaseAddress) + (RegOffset))</td></tr>
<tr class="memdesc:a11c28dcf104dea98ffe4e3eef0a600cb"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro reads a value from a SDI RX register.  <a href="#a11c28dcf104dea98ffe4e3eef0a600cb">More...</a><br/></td></tr>
<tr class="separator:a11c28dcf104dea98ffe4e3eef0a600cb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a863c6b811d56e05b84d81cbe84d14d0d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__sdirx__hw_8h.html#a863c6b811d56e05b84d81cbe84d14d0d">XV_SdiRx_WriteReg</a>(BaseAddress, RegOffset, Data)&#160;&#160;&#160;<a class="el" href="xv__sdirx__hw_8h.html#ad753096703e130b7080880ba43e8fde1">XV_SdiRx_Out32</a>((BaseAddress) + (RegOffset), (u32)(Data))</td></tr>
<tr class="memdesc:a863c6b811d56e05b84d81cbe84d14d0d"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro writes a value to a SDI RX register.  <a href="#a863c6b811d56e05b84d81cbe84d14d0d">More...</a><br/></td></tr>
<tr class="separator:a863c6b811d56e05b84d81cbe84d14d0d"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="a03ee5488e3a4741dbe0ca82423520d18"></a>
<div class="memitem">
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          <td class="memname">#define XV_SDIRX_HW_H_</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Prevent circular inclusions by using protection macros. </p>

</div>
</div>
<a class="anchor" id="a361bfcf74a8aa15417629343eccac197"></a>
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          <td class="memname">#define XV_SdiRx_In32&#160;&#160;&#160;Xil_In32</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Input Operations. </p>

</div>
</div>
<a class="anchor" id="aa01626b56f4a4bb197301ce06c17d33e"></a>
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          <td class="memname">#define XV_SDIRX_MASK_16&#160;&#160;&#160;0xFFFF</td>
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      </table>
</div><div class="memdoc">

<p>16 bit mask value </p>

</div>
</div>
<a class="anchor" id="ad753096703e130b7080880ba43e8fde1"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XV_SdiRx_Out32&#160;&#160;&#160;Xil_Out32</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Output Operations. </p>

</div>
</div>
<a class="anchor" id="a11c28dcf104dea98ffe4e3eef0a600cb"></a>
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          <td class="memname">#define XV_SdiRx_ReadReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;<a class="el" href="xv__sdirx__hw_8h.html#a361bfcf74a8aa15417629343eccac197">XV_SdiRx_In32</a>((BaseAddress) + (RegOffset))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This macro reads a value from a SDI RX register. </p>
<p>A 32 bit read is performed. If the component is implemented in a smaller width, only the least significant data is read from the register. The most significant data will be read as 0.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the SDI RX core instance. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset of the register (defined at the top of this file).</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The 32-bit value of the register.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="xv__sdirx__hw_8h.html#a11c28dcf104dea98ffe4e3eef0a600cb" title="This macro reads a value from a SDI RX register. ">XV_SdiRx_ReadReg(u32 BaseAddress, u32 RegOffset)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__sdirx_8h.html#a37c1e8a6ab909ce6fc5a546623949fa2">XV_SdiRx_Axi4sBridgeDisable()</a>, <a class="el" href="xv__sdirx_8h.html#a0568708b00564e79440715673275d4a4">XV_SdiRx_Axi4sBridgeEnable()</a>, <a class="el" href="xv__sdirx_8h.html#a5f6c968fc0726db4d20b65b6d0c59176">XV_SdiRx_ClearYCbCr444_RGB_10bit()</a>, <a class="el" href="xv__sdirx_8h.html#a21943b90cf4165fbe2994841fed37d0e">XV_SdiRx_DebugInfo()</a>, <a class="el" href="xv__sdirx_8h.html#a32162a162d8bd4c732bb6609a2b108b9">XV_SdiRx_FramerDisable()</a>, <a class="el" href="xv__sdirx_8h.html#a3f489d8879386783b5219b87fdfdffa6">XV_SdiRx_FramerEnable()</a>, <a class="el" href="xv__sdirx__intr_8c.html#a6914e6b029c6433c3e339fb350a8e6bb">XV_SdiRx_GetIntrEnable()</a>, <a class="el" href="xv__sdirx__intr_8c.html#a51f76f20ef6b9169790e73b79ccba859">XV_SdiRx_GetIntrStatus()</a>, <a class="el" href="xv__sdirx_8h.html#ac36464a3c528cb595b0ca975a5139df3">XV_SdiRx_GetPayloadId()</a>, <a class="el" href="xv__sdirx_8h.html#aee258ea49b5efc86d34ece895236a71a">XV_SdiRx_GetSdiMode()</a>, <a class="el" href="xv__sdirx__intr_8c.html#af464c662bc41fd9d6b3f3e07847ea9eb">XV_SdiRx_InterruptClear()</a>, <a class="el" href="xv__sdirx__intr_8c.html#aed746e1235a8a4799a8c61ec02a8f52b">XV_SdiRx_IntrEnable()</a>, <a class="el" href="xv__sdirx_8h.html#aa5e237f32f024f3faff39e35aa4cb117">XV_SdiRx_ReportDetectedError()</a>, <a class="el" href="group__v__sdirx.html#ga44f1120088e4da9b903c225f4610e830">XV_SdiRx_SelfTest()</a>, <a class="el" href="xv__sdirx_8h.html#ab94dfd6e8b78b704f5b9a16a2afb5840">XV_SdiRx_SetYCbCr444_RGB_10bit()</a>, <a class="el" href="xv__sdirx_8h.html#aea144b8a832fb5bfafbc9e1b54595b30">XV_SdiRx_Start()</a>, <a class="el" href="xv__sdirx_8h.html#ad8a5744b701842dd956d608cf4b8495f">XV_SdiRx_Stop()</a>, <a class="el" href="xv__sdirx_8h.html#a45742ac36579e38676885ea0528f9421">XV_SdiRx_VidBridgeDisable()</a>, <a class="el" href="xv__sdirx_8h.html#a497f29418b88c6ff0c04e391049c25c2">XV_SdiRx_VidBridgeEnable()</a>, and <a class="el" href="xv__sdirx_8h.html#ae4b6449c0758f5c3bd019a55dbf028bb">XV_SdiRx_WaitforPayLoad()</a>.</p>

</div>
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<a class="anchor" id="a2ed5f658c2cce95c1abff6f684b78532"></a>
<div class="memitem">
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          <td class="memname">#define XV_SDIRX_SHIFT_16&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>16 shift value </p>

</div>
</div>
<a class="anchor" id="a863c6b811d56e05b84d81cbe84d14d0d"></a>
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          <td class="memname">#define XV_SdiRx_WriteReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;<a class="el" href="xv__sdirx__hw_8h.html#ad753096703e130b7080880ba43e8fde1">XV_SdiRx_Out32</a>((BaseAddress) + (RegOffset), (u32)(Data))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This macro writes a value to a SDI RX register. </p>
<p>A 32 bit write is performed. If the component is implemented in a smaller width, only the least significant data is written.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the SDI RX core instance. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset of the register (defined at the top of this file) to be written. </td></tr>
    <tr><td class="paramname">Data</td><td>is the 32-bit value to write into the register.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__sdirx__hw_8h.html#a863c6b811d56e05b84d81cbe84d14d0d" title="This macro writes a value to a SDI RX register. ">XV_SdiRx_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__sdirx_8h.html#a37c1e8a6ab909ce6fc5a546623949fa2">XV_SdiRx_Axi4sBridgeDisable()</a>, <a class="el" href="xv__sdirx_8h.html#a0568708b00564e79440715673275d4a4">XV_SdiRx_Axi4sBridgeEnable()</a>, <a class="el" href="xv__sdirx_8h.html#a4a70cc2c30fe2cc5d5cb478159dbe5fa">XV_SdiRx_CfgInitialize()</a>, <a class="el" href="xv__sdirx_8h.html#a5f6c968fc0726db4d20b65b6d0c59176">XV_SdiRx_ClearYCbCr444_RGB_10bit()</a>, <a class="el" href="xv__sdirx_8h.html#a32162a162d8bd4c732bb6609a2b108b9">XV_SdiRx_FramerDisable()</a>, <a class="el" href="xv__sdirx_8h.html#a3f489d8879386783b5219b87fdfdffa6">XV_SdiRx_FramerEnable()</a>, <a class="el" href="xv__sdirx__intr_8c.html#af464c662bc41fd9d6b3f3e07847ea9eb">XV_SdiRx_InterruptClear()</a>, <a class="el" href="xv__sdirx__intr_8c.html#a3f7bbadf43e42e34a23a2fb23609dab7">XV_SdiRx_IntrDisable()</a>, <a class="el" href="xv__sdirx__intr_8c.html#aed746e1235a8a4799a8c61ec02a8f52b">XV_SdiRx_IntrEnable()</a>, <a class="el" href="xv__sdirx_8h.html#aeb19c921c0ff6ec2b60bdb6911bdc8d2">XV_SdiRx_SetEdhErrCntTrigger()</a>, <a class="el" href="xv__sdirx_8h.html#ab2a5fcb4ce17112434766264f92099ef">XV_SdiRx_SetVidLckWindow()</a>, <a class="el" href="xv__sdirx_8h.html#ab94dfd6e8b78b704f5b9a16a2afb5840">XV_SdiRx_SetYCbCr444_RGB_10bit()</a>, <a class="el" href="xv__sdirx_8h.html#aea144b8a832fb5bfafbc9e1b54595b30">XV_SdiRx_Start()</a>, <a class="el" href="xv__sdirx_8h.html#ad8a5744b701842dd956d608cf4b8495f">XV_SdiRx_Stop()</a>, <a class="el" href="xv__sdirx_8h.html#a45742ac36579e38676885ea0528f9421">XV_SdiRx_VidBridgeDisable()</a>, and <a class="el" href="xv__sdirx_8h.html#a497f29418b88c6ff0c04e391049c25c2">XV_SdiRx_VidBridgeEnable()</a>.</p>

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